Chip Design is a Loop, Not a Flow

When I was preparing for my NVIDIA interviews, I memorized the ASIC design flow.

Architecture. Microarchitecture. RTL. Verification. Synthesis. Floorplan. Place and route. Tapeout.

It’s a good mental model. But it misses something. Chip design isn’t a sequence of steps. It’s more like a massive search problem.

Fundamentally, chip design translates mathematical capabilities and SLAs down to silicon. But silicon imposes physical constraints: reticle area limit, memory shoreline availability, routing density, thermal limits, and foundry design rules.

This means that chip designers need to make numerous choices across different axes. Each choice interacts non-linearly with another making the decision space very combinatorially complex. The challenge is to search this space for designs that make right tradeoffs across performance, energy, area efficiency, and latency.

Seen this way, chip design is fundamentally a multi-objective search problem.

How have humans dealt with this so far

Humans make this search space tractable by decomposing it into levels of abstractions. Organizations are built around these abstractions because no one person can reason about the entire chip at once.

These abstractions enable specialization. RTL engineers focus on the behavior and implementation of a block, physical design teams hyperfixate on placement and routing, and network architects reason about topology. Each team searches a smaller, more manageable part of the overall design space and finds their own local minima.

But these subspaces aren’t independent. A local minima might mean a maxima elsewhere. Today, chip designers deal with this by inserting loops into bounded parts of the ASIC design flow.

Engineers propose a design, evaluate its downstream consequences, and revisit earlier decisions when necessary. The constraint is how many of these loops can be completed before tapeout.

Each loop consumes engineering time. As a result, we can only do a finite number of loops and teams can only explore a small fraction of the design space before committing to silicon.

AI changes the economics of search

AI changes the search process in two ways: it can make each iteration cheaper, and it can expand the portion of the design space we can practically search at once.

The first is straightforward. Today, many loops are bottlenecked on engineering time: proposing a change, running tools, interpreting results, and deciding what to do next. An AI agent can run overnight and use reasoning to do the same thing. This means we can run more loops within the same tapeout schedule.

The second implication is more interesting. AI may make some abstraction boundaries cheaper to cross. Abstractions exist to enable human comprehension. But they also determine which variables are exposed to optimization and which ones are treated as fixed. If AI can reason below and across these levels of abstractions, hidden variables become exposed.

Jalapeño offers an early software-side example of this idea. The mapping of matrix tiles to compute cores is normally abstracted away. According to Zartbot’s analysis, OpenAI exposed spatial mapping as a variable via the compiler and made AI search over it. In a 40-hour optimization run on a DeepSeek MLA kernel, the implementation progressed from a functionally correct baseline to 88.9% of the kernel’s theoretical hardware peak.

This is how I interpret Jeff Dean’s argument about the future of chip design. He describes replacing part of today’s 12-18 month design process with automated search.

The idea isn’t that AI enumerates every chip or that abstractions disappear. It’s that faster test-time search, combined with feedback that crosses abstraction boundaries, could build better chips faster.

Bottleneck 1: Representation & Formalization

Searching across abstraction levels requires an agent to understand how a decision made in one representation propagates to another. Unfortunately, each stage of the ASIC design flow has its own representation. Product requirements may be expressed in terms of latency or throughput, microarchitecture in terms of dataflow and RTL in terms of timing paths.

What’s lacking is a representation or ontology across these stages. This gap probably exists because of decades of specialized tooling and organizational inertia. Only recently have frontier AI chips needed to meet rigorous, end-to-end data center SLAs.

And more than representation, what enables rigorous search is formalization. A formal specification says, in a mathematically precise language, what must be true. If representation can be developed that captures equivalence across the different axes of chip design, search becomes much more effective as it’s correct by construction.

AlphaProof is a good analogy. It was able to achieve the silver medal in the IMO in 2024 precisely because DeepMind formulated math problems in Lean. But there was a crucial prerequisite: human experts manually formalized the problems before AlphaProof attempted them.

I foresee that this is going to be the work that faces chip design: documenting flows, standardizing tool outputs, and formalizing representations across layers of abstractions.

Bottleneck 2: Evaluation

Any search procedure needs fast, trustworthy feedback or rewards about which candidates are promising. The problem is that conventional EDA flows can be slow. This means that proxy rewards are all the more imperative. However, these proxies need to represent the final objective accurately, which is tricky.

Consider physical design. An early placement can cheaply estimate wirelength and congestion. But it doesn’t yet know the final routes or parasitics. Although you can argue that you don’t need to know this to plan out the overall network of the chip, it would be crucial in choosing the microarchitecture of a block.

So the challenge here is to not only build cheap evaluators but to determine which evaluator is sufficiently accurate for each decision in the search space and which combination of evaluator-decision pairs enable high fidelity results.

The Future

The near-term version of the future is much less dramatic than an autonomous agent producing a complete chip. I think it starts with engineers identifying bounded parts along the ASIC design flow where three things are true:

1. The system can make valid design changes automatically
2. The quality of those changes can be evaluated reliably
3. Evaluation is cheap and fast enough to repeat many times

When these conditions hold, AI can search this bounded space faster than humans. Eventually, as representations become better connected, these bounded loops can begin to interact and we can search across a wider search space.

Search could then operate across boundaries that humans currently find difficult or expensive to cross. And over time, the results of test-time search could become training data. Rather than rediscovering the same tradeoffs, RL can train policies to make future search more efficient.